RISC vs CISC ·
C = A + B
· Execution Model
RISC
CISC
Live cycle accounting
Instruction
—
Stage
—
Cycles this instr.
—
Cumulative cycles
0
Assumptions load on architecture select.
⟲ Reset
Step →
▶ Play
Run Both & Compare
0
CYCLES ELAPSED
0.0 ns
CPU TIME (EST.)
–
AVG CPI
Select RISC or CISC, then Step or Play to watch the instruction sequence execute.
Performance Comparison — this scenario only
Same task (C = A + B), same assumed clock, different instruction count & CPI.
CPU Time = Instruction Count × CPI × Clock Cycle Time
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